I had the same kind of NTT-in-the-hot-path mess when I shipped a prototype verifier on a tiny FPGA box, and the thing only failed once we started feeding it the weirdest points in the ring, where the carry wrapped one limb later than my test vectors expected. Took me an afternoon with a notebook and a dump of the twiddle schedule to find the off-by-one hiding in the reduction step, which was annoyingly similar to the sort of bug that only shows up when the proof is already packed and the chain is live.