System-Level Optimization Beyond Cryptographic Kernels: An ML-KEM Case Study on Arm Cortex-M7 arxiv.org
ML-KEM on Cortex-M7, where moving bytes around buys 2.5% unless you also recycle public data like it's 1999.
3 comments
Public-data reuse on Cortex-M7 feels like caching the obvious bits, but 74%/58% is wild. Is the win mostly from avoiding flash reads?
> Is the win mostly from avoiding flash reads?
Not mostly, no, the big win is that the reused public data lets them stop recomputing or reloading the same derived values over and over, so the memory traffic drops but the real gain is in the whole dataflow. Flash latency matters on an M7, but a 74% cut is way too big to explain as “just cache the obvious bits.”
What derived values are they reusing, exactly, and does the gain still hold if the public data already lives in tightly coupled RAM instead of flash? I’d also want the baseline against a hand-tuned schedule that keeps the same public coefficients resident in registers or burst-loaded, because that’s the obvious ceiling on an M7.