Post-training defense for analog in-memory accelerators, maps around process faults and power leakage without retraining.

Can a Halo2 zkVM prove synthesized hardware is power-side-channel safe without leaking the netlist? Apparently, yes.

First-order DPA-hardened ML-DSA on Pavona ACC, with bitsliced masking tricks and benchmarks for ML-DSA-44/65/87.

First-order masked ML-DSA keygen/signing for Pavona ACC, reusing masked KMAC and aiming at DPA resistance?

Rejection sampling, the old side-channel workhorse, beats CDT here with fewer masked ANDs for lattice Gaussians (incl. HAWK).

MIT CSAIL profile of Srini Devadas's 2026 Eckert-Mauchly Award, with his work on secure processors, PUFs, and PAC Privacy.

A composable leakage framework for adaptive observers, finally unifying transcripts, timing, cache, power, and EM without ad hoc glue.

Ledger ports ML-KEM/ML-DSA into its SDK, proving the NIST PQ stack can fit in a secure element if you shave hard enough.

Can conjugating a block cipher really cut multiplications? This paper says yes, with SKINNY getting leaner.

How little sign leakage breaks Falcon, HAWK, and ML-DSA? Apparently enough to turn key recovery into halfspace learning.

Survey of deep-learning hardware side channels, mapping leakage to model, weights, and inputs, then the usual countermeasure laundry list.

Can stray RF emissions really fingerprint which app you tapped? This paper says yes, forensics-style.

HPCC gives single-cycle masked 3-input multiplies and 2-cycle AES S-boxes in the PINI glitch model.

Bare-metal ATmega328P auth engine in AVR asm, with Speck, CTR, MAC checks, and a tiny decrypted bytecode interpreter.

Two smartphones do off-axis acoustic plus magnetic G-code theft from 3D printers, because confidentiality is optional.

Is this an automotive PQC roadmap, or just a chip vendor turning quantum into a buzzword? TPMs, HSMs, ASICs, ISO 21434.

Can FPGA parallelism still rip masked ML-KEM verification apart? This paper says yes, even when microcontrollers look safer.

First-order masking still folds to second-order CPA on masked Kyber768 on Cortex-M4, with leakage models and SNR plots.

GlobalPlatform’s Pavona is an open silicon distro with PQC, root-of-trust IP, and the usual certification paperwork.

A paper on how LLM-assisted PQC work slowly drifts from constant-time discipline, then tries to gamify the fix.

Can hardware-guided patching actually fix runtime side channels without over or under-shooting? DISARM says maybe.

Paper on MIPS timing side channels in embedded CPUs, with cache and execution-engine leakage, because routers needed more drama.

obliv-clang adds compile-time obliviousness checks to C++, including nested pointers, which is more than the usual toy subset.

First-order masked ML-KEM for Pavona's ACC fits under 22 KB DMEM and costs 2.6x to 3.4x, because side channels insist.

Paper on AMNC for 3D printers: acoustics get killed, vibrations still leak enough to keep the attack alive, naturally.

OTRO swaps the usual tokenizer side-channel mess for square-root ORAM plus replicas, aiming to keep TTFT tolerable.

Can you brick a CUDA collective by flipping its masks, lanes, or epochs? This paper says yes, then adds CICs.

Embedded PQC gets the usual laundry list, but here the point is hardware pain: RAM, bandwidth, no accelerators, and hybrid stopgaps.

SoK on constant-time models, plus an attack that finds private-key loading leaks in OpenSSL and BoringSSL outside the primitive.

PR adds fully masked ML-KEM decaps/keygen plus masking gadgets for Pavona's crypto coprocessor, with the usual register fuss.