ARMOR-IMC: Adaptive Resource Mapping for Operational Robustness via Secure In-Memory Computing arxiv.org
Post-training defense for analog in-memory accelerators, maps around process faults and power leakage without retraining.
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01 02 Can you trust Opal2 SEDs on Linux? This black-box study of 38 drives says firmware bugs and incompatibilities say no.03 SEALSQ and Quobly Sign $5 Million Commercial Agreement to Integrate Post-Quantum Security into Next-Generation Silicon Quantum Computing Platforms crweworld.comA $5M press-release handshake to bolt post-quantum root-of-trust hardware onto silicon quantum computers.04 SEALSQ and Quobly Sign $5 Million Commercial Agreement to Integrate Post-Quantum Security into Next-Generation Silicon Quantum Computing Platforms globenewswire.comPress release on a $5M deal to bolt PQ security onto Quobly's silicon quantum stack, because quantum needs more quantum.05 SEALSQ and Quobly Sign $5 Million Agreement to Secure Silicon Quantum Computers thequantuminsider.comSEALSQ and Quobly ink a $5M deal to bolt post-quantum security onto silicon quantum hardware.06 Can a Halo2 zkVM prove synthesized hardware is power-side-channel safe without leaking the netlist? Apparently, yes.07 SEALSQ and Quobly Sign $5 Million Commercial Agreement to Integrate Post-Quantum Security into Next-Generation Silicon Quantum Computing Platforms cioinfluence.comSEALSQ and Quobly announce a $5M deal to bolt post-quantum root-of-trust onto silicon quantum hardware, because why not.08 SEALSQ and GlobalFoundries Partner to Accelerate Post-Quantum Cryptography and Quantum Computing Technologies nasdaq.comPress release on SEALSQ and GlobalFoundries teaming up for PQC IP, HSM chiplets, and cryogenic CMOS, because buzzwords breed.09 SEALSQ, GlobalFoundries Partner on Post-Quantum Cryptography and Quantum Computing newnetworktimes.comSEALSQ and GlobalFoundries sign an MoU for PQC IP, chiplet HSMs, and cryogenic CMOS, because plain chips are passé.10 SEALSQ and GlobalFoundries Partner to Accelerate Post-Quantum Cryptography and Quantum Computing Technologies sealsq.comSo is this a chip deal for PQC, secure chiplets, and cryogenic CMOS, or just another MoU with a quantum sticker?11 SEALSQ and GlobalFoundries Partner to Accelerate Post-Quantum Cryptography and Quantum Computing Technologies globenewswire.comCryogenic CMOS and post-quantum IP, via a memorandum of understanding, because chip PR now needs quantum too.12 SEALSQ and GlobalFoundries Partner to Accelerate Post-Quantum Cryptography and Quantum Computing Technologies - Semiconductor Digest semiconductor-digest.comA PQC partnership press release, except it also pitches secure chiplets and cryogenic CMOS for quantum hardware.13 MIT CSAIL profile of Srini Devadas's 2026 Eckert-Mauchly Award, with his work on secure processors, PUFs, and PAC Privacy.14 EigenQ Announces Post-Quantum Security Readiness Capabilities for Existing In-Field Intel Xeon-Based Systems cioinfluence.comCan your old Xeons do PQC? EigenQ says yes, with CNSA 2.0 migration bits for deployed boxes.15 The nasty bit is the hardware root of trust, apparently, is the thing that broke, and TEEs may not have a real fix.16 Your standard cells can be the Trojan, and this paper scores how hard it is to notice before tapeout.17 TPMs, HSM chiplets, and quantum-resistant ASICs for cars, because software-defined vehicles needed one more acronym stack.18 DV Club Zurich 2026 talks and slides on verifying RISC-V, SoCs, crypto extensions, and connected devices, because silicon loves bugs.19 Can FPGA parallelism still rip masked ML-KEM verification apart? This paper says yes, even when microcontrollers look safer.20 IEEE Spectrum on Pavona, an open-hardware push for modular security chips and OpenTitan designs, because hardware needed more committees.21 GlobalPlatform Launches Pavona: The First Open Silicon Distribution with Production-Grade Post-Quantum Cryptography pavona.orgGlobalPlatform’s Pavona is an open silicon distro with PQC, root-of-trust IP, and the usual certification paperwork.22 Chiplet security paper says the new bit is an active interposer root of trust, not another “trust the package” wish.23 Can gem5 do guided RISC-V fault injection? InjectV says yes, for registers, memory, and FISSC benchmarks.24 Press release for a layered SoC security stack, analog tamper sensors plus Xiphera’s PQC cores, because RSA wasn’t enough.25 5G privacy paper: vSIM profiles decouple device and subscriber IDs, with an FPGA/srsRAN prototype and re-ID tests.26 AMD quietly yanks TSME from some consumer Ryzen parts, so Linux users found their RAM no longer gets the usual cheap at-rest crypto.27 Announcement of Agile Analog and Xiphera's PQC plus anti-tamper SoC security stack, because one layer apparently wasn't enough.28 AMD apparently yanks TSME from consumer Ryzen, leaving the ciphertext to PRO and EPYC where it always wanted to be.29 DSA-2026-197: Security Update for Dell Client Platform BIOS for a Weak Encoding for Password Vulnerability dell.comWeak password encoding in BIOS, the kind of thing you hope died with 2003, gets a Dell client platform advisory and patch.30 Apple takes PCC off its own silicon, moving confidential inference to Google Cloud with TDX, Titan, and attestation theater.