TranScope: What the Software Hides About LLM Training Data, the Hardware Reveals at Scale, and Accelerators Magnify arxiv.org
Constant-time LLMs still leak training membership via TLB/page-table quirks, courtesy of tokenization.
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01 02 Can a perceptron catch Spectre before the secret leaks, or is this just another hardware watchdog with homework?03 Mission-Aware Attestation Envelopes for Time-Critical Autonomous Action: A Hardware-in-the-Loop V2I Study arxiv.orgHardware-in-the-loop V2I study of TPM-backed attestation, where stale evidence and slow verification break real-time autonomy.04 Why can't you just brute-force an iPhone passcode? The Secure Enclave adds hardware keys, delays, and lockouts.05 Infineon’s PSOC™ Control C3 Performance Line sets a new standard for real-time control and PQC security international.electronica-azi.roInfineon's PSoC Control C3 MCUs do real-time power and motor control, then add PQC, secure boot, and update checks for garnish.06 Future Cybersecurity: Hardware Memory Safety, Automated Governance and Post-Quantum Cryptography infoq.comHardware memory safety and SBOMs: an InfoQ chat that treats post-quantum migration like the operational tax it is.07 The Achilles' Heel of Partial Reconfiguration: Optical Side-Channel Leakage on the 7-Series ICAP arxiv.orgNot just bitstream protection in the abstract, they break AMD's 7-Series partial-reconfig scheme by reading ICAP optically.08 CNSA 2.0 shows up in an FPGA blog post, with Mach-N2 pitching PQC, attestation, and secure control.09 Fortanix’s 10-year confidential-computing retrospective, from SGX to TDX, SEV-SNP and CCA, plus the usual trust theater.10 O(N) frame-rate estimation from EM side channels, using display resolution as the shortcut the autocorrelation folks forgot.11 SEALSQ Leverages NIST FIPS 140-3 Level 3 Validation to Accelerate Government, Critical-Infrastructure and Post-Quantum Hardware-Security Programs; Provides Updated Certification and Commercialization Timetable crweworld.comPress release on SEALSQ's FIPS 140-3 L3 validation and PQ hardware roadmap, because certification is the product now.12 Assessing Runtime Electromagnetic Detection of CPU Hardware Trojans Targeting Kernel Memory arxiv.orgThe surprise is a trojan that writes kernel memory getting caught from runtime EM noise on RISC-V, because silicon spills.13 Analyst piece on Lattice's Mach-N2, pitching CNSA 2.0 PQC plus flash/root-of-trust as the thing rivals forgot.14 SEALSQ Leverages NIST FIPS 140-3 Level 3 Validation to Accelerate Government, Critical-Infrastructure and Post-Quantum Hardware-Security Programs; Provides Updated Certification and Commercialization Timetable ca.finance.yahoo.comSEALSQ says its VaultIC408 got FIPS 140-3 L3, the usual certificate flex for a secure element with PQC ambitions.