Paper on self-tuning ring-oscillator TRNGs and long-term stability, with NIST tests, because entropy still needs babysitting.

First-order DPA-hardened ML-DSA on Pavona ACC, with bitsliced masking tricks and benchmarks for ML-DSA-44/65/87.

Pipelined FPGA post-processing for QKD, trading logic for throughput and resource efficiency like crypto hardware loves to do.

Survey of deep-learning hardware side channels, mapping leakage to model, weights, and inputs, then the usual countermeasure laundry list.

HPCC gives single-cycle masked 3-input multiplies and 2-cycle AES S-boxes in the PINI glitch model.

Most PQC car talk stops at firmware, this one wants it in TPMs, HSM IP, chiplets, and a future QASIC.

A federal quantum deadline is back, with DOE told to chase a fault-tolerant machine by 2028 and PQC migration sped up.

Apparently hardware benchmarks need Merkle receipts, every number is tied to an append-only evidence graph.

Pavona is an open-source silicon distro with tapeout-proven blocks and hardware-first CI, not just another IP graveyard.

Workshop CFP for encrypted AI, covering FHE, MPC, ZK, and the usual stack of accelerators, compilers, and deployment pain.

ISCA 2026 Cryptolets tutorial page, for the open hardware answer to one-off crypto accelerators: chiplets, flows, and benchmarks.

Xiaomi's MJA1 secure chip gets probed via I2C sniffing, flash dumps, and firmware RE, with its command/CRC scheme reconstructed.

First-order masked ML-KEM for Pavona's ACC fits under 22 KB DMEM and costs 2.6x to 3.4x, because side channels insist.

DSP-free FrodoKEM hardware, with blockwise matrix-mul and CSA Wallace trees, claims 2.5x over prior FPGA/ASIC designs.

Embedded PQC gets the usual laundry list, but here the point is hardware pain: RAM, bandwidth, no accelerators, and hybrid stopgaps.

PR adds fully masked ML-KEM decaps/keygen plus masking gadgets for Pavona's crypto coprocessor, with the usual register fuss.