Loongson CPUs can leak L1 cache into FP/vector regs, and this site lays out the bug, PoCs, impact, and mitigations.
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01 02 Governing the KV Cache: Preventing Timing Side-Channel Leakage in Multi-Tenant LLM Inference arxiv.orgKV cache timing leaks in multi-tenant LLMs, with KVGov adding per-principal salted keys and auditing to blunt the usual cache side channels.03 SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon arxiv.orgPaper on CPU-to-GPU SLC side channels in Apple Silicon, with cache indexing reverse engineering and attacks on GNNs/LLMs.